1. Field of the Invention
This invention relates to the field of level shifter circuits for use between voltage domains, such as, for example, different voltage domains within an integrated circuit.
2. Description of the Prior Art
A level shifter circuit is used when there is a need to pass signals from one voltage domain to a different voltage domain. Typically, such multiple domain arrangements were not used in high performance systems due to the increased complexity and the relatively long latency which is associated with level shifter circuits.
A trend within integrated circuits is the increasingly common use of embedded SRAM memory. With the reduction in size of process geometries, such SRAM cells are becoming less stable. In order to enhance the stability of SRAM provided on-chip, and still achieve low power for the processor, there is an increasing need for the SRAM and the processor to use different voltage supplies from different domains. As an example, embedded SRAM may use a higher voltage supply to guarantee state retention whilst the rest of the system including the processor may use a lower voltage supply to reduce power consumption. In order to maintain the performance of the processor, and to reduce switching power, level shifters are provided to pass signals between these domains. These level shifters should have a low latency and a low switching (crow-bar) power. Such level shifters should also have a low circuit area overhead.
FIG. 1 of the accompanying drawings schematically illustrates the basic concept of a level shifter circuit. This comprises a first inverter 2 operating in a low voltage domain and a second inverter 4 operating in a high voltage domain. A problem with this simple arrangement is that the desirable situation of a low static power consumption is difficult to achieve within the second inverter 4 since the signal from the first inverter 2 at the VDD level of the first domain is ineffective at completely switching off the transistors within the second inverter 4 given its higher VDD level. In addition, the current during switching of the second inverter 4 is undesirably high.
FIG. 2 of the accompanying drawings shows a known level shifter seeking to address some of the limitations of the level shifter of FIG. 1. In this level shifter circuit, a feedback PMOS 6 is provided to boost the voltage at node 8 to the value of the HighVDD. This provides a reasonable solution to limiting the power consumption. However, the circuit of FIG. 2 suffers from a limited range of voltage level shifting within which it may operate since the input inverter 10 may not be strong enough to overcome the action of the feedback PMOS 6 if the low voltage domain is operating at a significantly lower VDD level than the high voltage domain. In addition, the operational range of this level shifter circuit depends upon process variation concerning the PMOS to NMOS ratio. Furthermore, the latency of the level shifter circuit can vary significantly based upon the process variation and the range of VDD being switched between.
FIG. 3 illustrates a possible enhancement over the circuit of FIG. 2. In this circuit a pair or cross-coupled PMOS transistors 12, 14 is used to provide a feedback circuit to boost the voltage at node 16 to the HighVDD level when appropriate. When the input to the level shifter circuit 20 is a “1”, the NMOS transistor 8 will turn on and in turn force the voltage at node 16 low. This turns on PMOS transistor 14, which turns off PMOS transistor 12 and then drives a high value of “1” out through the inverter 22. When the input to the NMOS transistor 18 is a “0”, the inverter 24 will switch its output to a “1”, which in turn will switch on the NMOS transistor 26, switch on the PMOS transistor 12, drive the node 16 to the full voltage of the high VDD domain via the PMOS transistor 12 and switch off the PMOS transistor 14. The high voltage level at node 16 will be inverted by the inverter 22 and result in a output value of “0” being drive out from the inverter 22. A significant disadvantage of the circuit of FIG. 3 is that it has a disadvantageously long latency since it is necessary when the input is changed to a “0” for this change to propagate through four levels of transistors, namely through inverter 24, NMOS transistor 26, PMOS transistor 12 and inverter 22.